1. Field of the Invention
This invention relates generally to low-power operating modes of electronic devices, and, more particularly, to a method and apparatus for transitioning between multiple power saving modes of operation.
2. Description of the Related Art
For a variety of reasons, power consumption has become an increasingly significant issue for electronic devices such as computer systems. First, the United States has promulgated a number of regulations regarding power usage or power savings. Further, since many electronic devices, such as laptop computers, draw power from a battery, reducing power consumption can result in significantly longer usage, making these electronic devices more versatile and useful. Additionally, power consumption is related to the amount of heat produced by the electronic device. Reducing power consumption reduces the amount of heat generated, and, thus, reduces the size and complexity of heat sinks, fans, and other structures used to help cool the electronic devices. Accordingly, reducing power consumption can result in reduced costs by eliminating or scaling back the cooling structures. Additionally, reduced heat dissipation generally means that electronic components may be more densely packed, leading to smaller, more compact packages. Moreover, reducing power consumption is environmentally friendly, as it reduces the use of fossil fuels and attendant pollutants.
Accordingly, the electronics industry has been driven to develop a variety of power saving schemes. Computer systems and other electronic devices frequently have a low-power mode of operation that is implemented using different techniques. These low-power modes primarily take advantage of the fact that most computer systems are not always working at high capacity, but routinely have periods of time where they are essentially idle. Some computer systems reduce power by reducing the power consumed by certain components used in the system during these idle periods of time. For example, many computer systems employ a monitor, which consumes substantial power. Thus, during low-power mode, the system may turn the monitor off. Likewise, other components, such as a hard disk drive, compact disk (CD) player, random access memory (RAM), and the like may also be turned off. Significant power savings may be achieved by removing power from the presently unused peripheral devices. However, when a user attempts to operate a computer system that has its peripheral devices powered-down, a significant delay occurs before the computer system can restore power to the peripherals and begin responding to the requests of the user. Thus, many users bypass or otherwise disable these types of low-power operating modes to avoid these delays.
Other power saving schemes reduce the frequency of a clock signal supplied to components used in the computer system. All other factors being equal, reducing the clock frequency generally proportionally reduces power consumption. Thus, some systems reduce the clock frequency by a significant factor, such as by one-half or more to achieve significant power savings. Normally, however, the various subsystems within a computer system must have a globally synchronized clock signal to insure proper operation. This synchronization is commonly achieved using a phase-locked-loop (PLL) circuit. PLL circuits, however, have a finite frequency range in which they operate with sufficient speed and accuracy to insure that a globally synchronized clock signal may be maintained. Thus, where the clock frequency is changed dramatically, such as by half or more, the PLLs may operate marginally or erratically. Faulty operation of the PLLs may produce unstable operation of the computer system as a whole, causing the system to crash or lock-up. Thus, during transitions from normal to low-power mode, or vice versa, the system may fail, again encouraging the user to disable the power saving feature.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.
In another aspect of the present invention, a method for controlling a memory system is provided. The method is comprised of generating a first clock signal having a first preselected frequency in a first operating mode and a second preselected frequency in a second operating mode. The first clock signal is delivered to a phase lock loop circuit to produce a synchronized second clock signal to said memory. The second clock signal is delivered to the memory in the first operating mode, and the first clock signal is delivered to the memory in the second operating mode.